The present invention covers a scheme for having alignment checks controlled by "mode bits" within a microprocessor. Using this concept, the programmer is allowed to select whether a fault will be generated if a memory reference is to a misaligned address. The currently preferred embodiment of the present invention if incorporated in the architecture of the Intel 80486 microprocessor, also known as the i1486.TM. processor. The i486.TM. microprocessor is an improvement over Intel's 80386 microprocessor, also referred to as the 386.TM. processor. (Intel, 80386, 386, 80486, and 486 are trademarks of Intel Corporation).
The 80486 microprocessor is a 32-bit, high-performance member of the x86 family of processors. It is object code compatible with the 80386 processor. As a result it can run code developed for the previous members of the family. Generally, it is a reimplementation of the 80386 architecture with the aim of providing at least a 2.5 times performance improvement as measured by the average number of clocks per instruction. The present invention represents one such feature of the 80486 microprocessor which contributes to this performance improvement.
As mentioned above, this invention adds the capability to a microprocessor of being able to select whether a fault is generated if a memory reference in a program is to be misaligned address. Conventionally, an address of a datum is considered aligned if it is a multiple of its length. A one-byte datum is always aligned. A two-byte datum is aligned is its address is a multiple of two. A four-byte datum is aligned if its address is a multiple of four, and so on. Data, therefore, is generally aligned when the address is a multiple of its size.
The significance of aligned memory references becomes more evident when one considers the internal memory architecture of a microprocessor. In most computers the memory is organized in such a way that the data size is equal to the memory width. If you have a memory organized by 32-bits, this means that you can access a 32-bit item that has an address which is a multiple of four within one memory clock cycle. (A 32-bit word is frequently referred to as a doubleword or dword--a dword being comprised of four separate bytes, e.g., 0, 1, 2 and 3). Both the 80386 and the 80486 CPUs permit referencing to data at arbitrary addresses. If the reference is not aligned then the microprocessor suffers a performance penalty which is manifested by additional memory cycles needed to access or reference the data.
Consider a memory reference to a 32-bit dword beginning at address 3. In past approaches, the processor would reference 2 dwords; first the dword beginning at address 0 to extract byte 3, then the dword beginning at address 4 to extract the remaining bytes 4, 5 and 6. After accessing the required bytes the processor would then somehow piece them together to reconstruct the data item or memory reference. Thus, prior approaches suffer at least two penalties: (1) the requirement of at least two additional memory cycles, and (2) a reconstructing or "piecing together" of the data item in a new storage location.
To avoid this drawback, several alternative approaches have been attempted. For instance, in the 80386 alignment checks can be performed by the insertion of an in-line code proceeding every memory reference. This code generates an address into a register and then masks out the lower bits of the register. The masking operation is implemented by taking the same register components and adding an aligning displacement. Basically, a series of three separate instructions must be executed proceeding every memory reference using this approach. Since half of the instructions in a typical program reference memory in some way, this represents an unacceptable overhead--degrading performance as much as 20 to 30 percent.
Several machines, the most notably the new RISC processors, require all memory references to be aligned. These machines always fault on references to misaligned data. However, the faults are not selectable, so that faults are invariably generated. This presents a problem since many non-artificial intelligence environments (especially COBOL) benefit from the ability to reference misaligned data. Another category of machines permits misaligned references, however, with the performance penalty described above. These machines include the Intel 80386, Digital's VAX and the IBM 370. Consequently, a new method of providing optional misaligned address faults, which does not suffer from the performance penalties described above, is what is needed in the field.
As will be seen, the present invention provides a means for alignment checking which is selectable by the user and requires no additional instructions. Moreover, the invention supports two levels of masking for the alignment checking procedure; one at the application level and the other at the operating system level. With the ability to mask the trap or the fault itself, this invention offers the user two opportunities to control alignment checking.
Accordingly, the object of the present invention is to provide a means for detecting inadvertent misalignment of data. For purposes of program debugging, aligning data can increase performance substantially.
Another object of the present invention is to provide a means for generating alignment faults in certain artificial intelligence (AI) programs which use lower order address bits to identify types of pointers, and then use small displacements to "adjust out" these tag bits to get an aligned address. The present invention provides pointer type checking without a substantial performance penalty. Experimental measurements indicate that the present invention realizes a thirty percent performance boost on average AI programs running on the 80386 microprocessor. Other studies have shown a twenty percent increase on other machines.